Design Verification Engineer

Job Summary:**

CYIENT SEMICONDUCTORS PRIVATE LIMITED is seeking a skilled Design Verification Engineer to join our dynamic team. This role involves developing and executing comprehensive verification plans to ensure the functional correctness and quality of complex semiconductor designs.

Job Responsibilities:**

* Develop and implement robust verification test plans and test benches for complex digital and mixed-signal designs.
* Create and execute verification test cases using various methodologies (e.g., UVM, Specman, Vera, SystemVerilog).
* Perform functional and formal verification to identify and debug design flaws.
* Analyze coverage metrics (code, functional, assertion) and drive improvements to achieve verification closure.
* Collaborate closely with design engineers to understand specifications and contribute to design quality.
* Develop and maintain verification environments and automation scripts.
* Participate in design reviews and provide constructive feedback.
* Generate detailed verification reports and documentation.
* Stay updated with the latest verification methodologies, tools, and industry trends.

Job Qualifications:**

* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
* 2+ years of experience in ASIC/SoC design verification.
* Strong proficiency in SystemVerilog, UVM, and other industry-standard verification languages/methodologies.
* Experience with advanced verification techniques such as assertions (SVA), formal verification, and constrained-random verification.
* Familiarity with scripting languages like Perl, Python, or Tcl.
* Knowledge of digital design principles and computer architecture.
* Experience with industry-standard EDA tools (simulators, waveform viewers, debuggers).
* Excellent problem-solving, analytical, and debugging skills.
* Strong communication and interpersonal skills, with the ability to work effectively in a team environment.
* Prior experience with pre-silicon verification of complex IP blocks or SoC subsystems is highly desirable.