Design Verification Engineer

1. DV  GLS (10+ yrs | 2 Positions)
Must-Have: GLS & SDF timing validation, STA + CDC/RDC debug, Low-power & DFT validation
General: SV/UVM, Simulation tools, Automation
2. DV – GPU (5+ yrs | 1 Position)
Must-Have: GPU verification, Performance validation, Cache/coherency + NoC integration
General: SV/UVM methodology, Simulation tools, AMBA protocols

3. DV – ARM IPs (5+ yrs | 1 Position)
Must-Have: ARM CPUSS verification, CHI coherency & interconnect protocols, ARM subsystem debug/bring-up
General: SV/UVM, Simulation tools, AMBA protocols, ARM System Ready Compliance
4. DV – Ethernet (5+ yrs | 1 Position)
Must-Have: Ethernet protocol & compliance verification, SerDes/controller validation, UVM env development
General: SV/UVM, Simulation tools, AXI/APB

5. DV – Infrastructure (10+ yrs | 1 Position)
Must-Have: DV infra & regression management, Automation scripting (Python/Perl/Bash), CI/CD flows
General: Simulation/emulation, Build systems, Tool optimization
6. DV – SoC Integration-1 (8+ yrs | 2 Positions)
Must-Have: SoC bring-up (reset/clock/power/debug), CoreSight + JTAG/Scan, Multi-die validation
General: SV/UVM + firmware, AMBA protocols, ARM System Ready Compliance
7. DV – SoC Integration-2 (8+ yrs | 2 Positions) 
Must-Have: PCIe/CXL datapath & coherency, High-throughput traffic validation, Multi-chip systems
General: SV/UVM, AXI/NoC, Debug & trace
8. DV – Modeling (8+ yrs | 1 Position)
Must-Have: C++ bit-accurate modeling, FP/quantization (FP8/BF16/INT), Model-RTL correlation
General: Debug tools, UVM integration, Perf/accuracy trade-offs

1) Contract Duration - minimum 2 years2) Interview rounds and pattern - virtual and final F2F3) Work mode - 5 days work from office. Office location is Whitefield, Banglaore4) Shift timings  - Regular