Design Verification Engineer

About the Role

We’re looking for a highly experienced Design Verification Engineer to architect, deploy, and maintain advanced pre-silicon verification environments and automated verification flows to achieve sign-off quality using UVM and SystemVerilog .

This is a senior individual contributor / technical expert role with no team-lead or people-management responsibilities. The focus is on deep technical execution, verification architecture, and solving complex hardware verification challenges.

You’ll work closely with chip architects, RTL/VLSI design, Design, and Platform Integration teams within an advanced development environment, using modern verification methodologies and EDA tools to identify, debug, and resolve complex hardware issues.

Key Responsibilities

• Design, build, optimize, and maintain scalable and reusable UVM verification environments .
• Develop and maintain verification infrastructure for module-level and subsystem-level hardware blocks.
• Integrate high-level, bit-accurate C++ reference models as golden references within UVM environments.
• Apply modern verification methodologies, including:
• Assertion-Based Verification (SVA)
• Coverage-Driven Verification (CDV)
• Formal property checking
• Develop internal verification tools and advanced scripting infrastructure.
• Build and maintain automated regression and CI/CD flows , including GitLab CI.
• Contribute to the overall verification methodology and technical direction as an individual contributor.
• Review verification plans and define infrastructure metrics to drive verification closure.
• Track and analyze functional coverage, code coverage, and formal proofs.
• Collaborate with architecture, RTL/VLSI, design, and platform integration teams.
• Identify, debug, and support resolution of complex hardware anomalies.
• Contribute to verification sign-off for complex ASIC/SoC designs.

Required Experience & Technical Skills

• Engineering degree or equivalent technical education.
• 10–20+ years of hands-on ASIC/SoC Design Verification experience using UVM and SystemVerilog.
• Candidates with 15–20 years are particularly aligned, while exceptionally strong candidates with 10+ years may also be considered.
• The following are mandatory :
• UVM
• SystemVerilog
• Formal property checking / formal verification
• C/C++
• Experience with modern front-end IC simulation and verification tools such as Questa and/or Xcelium .
• Experience with both unit/module-level and subsystem/full-chip verification .
• Strong experience working on complex ASIC or SoC designs.
• Strong infrastructure automation experience using tools such as:
• Python
• SCons
• Make/Makefiles
• Git
• Experience developing automated flow generation, regression management, and data-parsing infrastructure.
• Strong system-level understanding of complex hardware designs.

Nice to Have

• Advanced Assertion-Based Verification / SVA expertise.
• Experience with both Questa and Xcelium.
• Python expertise beyond basic scripting.
• SCons/Make build and automation experience.
• GitLab CI experience.
• Experience verifying SoCs in the communications domain.

What Makes This Role Different

This is a deep technical IC position , not a people-management role. You’ll have the opportunity to work at the verification architecture and sign-off level while contributing directly to complex ASIC/SoC development.

You’ll be expected to operate independently, solve technically challenging verification problems, and contribute to scalable verification infrastructure and methodology.

Location

• Based in Israel .
• Candidates already located in Israel are strongly preferred.
• Relocation may be considered for an exceptional candidate.

Compensation

• Base salary: 40,000–50,000 ILS/month.
• Annual bonus: 7.5% of annual salary at this experience level.
• Sign-on grant: Free company shares.