Design Verification Engineer

Overview

We are seeking a highly skilled Design Verification Engineer to take full technical ownership of block-level verification for complex ASIC/SoC designs.

The ideal candidate must have a proven track record of architecting and building complete UVM testbench environments from scratch. While experience with high-speed protocols (UCIe, PCIe, Ethernet) is highly desirable, demonstrated expertise in end-to-end UVM testbench development is the primary requirement for this role.

Key Responsibilities

• Block-Level Ownership: Take full technical ownership of verification for 4–5 complex design blocks per project.
• Testbench Architecture: Design, build, and maintain robust verification environments from scratch using SystemVerilog and UVM (including testbench infrastructure, agents, drivers, monitors, sequencers, test sequences, scoreboards, and functional coverage models).
• Test Execution & Coverage: Develop and execute both directed and constrained-random tests; drive functional and code coverage closure.
• Debug & Regression: Perform detailed root-cause analysis, waveform debugging, protocol debugging, and regression triage.
• Integration & Collaboration: Work closely with customer engineering teams and internal project leads to ensure seamless integration of block-level verification into customer-owned top-level testbenches.

Required Qualifications & Technical SkillsCore Requirements (Must-Have)

• Experience: 6–10+ years of hands-on ASIC/SoC digital verification experience.
• UVM Expertise: Expert-level proficiency in SystemVerilog and UVM, with hands-on experience building end-to-end UVM testbenches completely from scratch.
• Methodology: In-depth mastery of constrained-random testing, functional coverage modeling, and automated regression flows.
• Tooling: Strong proficiency with industry-standard simulators (Synopsys VCS, Cadence Xcelium, or Siemens/Mentor Questa).
• Soft Skills: Excellent communication, proactive problem-solving, and the ability to work independently in a customer-facing, collaborative environment.

Preferred Protocol & Domain Experience (Strong Plus)

• Experience verifying complex digital designs in networking silicon, switches, NICs, or high-performance interconnect ASICs.
• Hands-on protocol experience with one or more of the following:
• UCIe (UCIe 2.0 preferred)
• PCIe (Gen 4 / 5 / 6)
• Ethernet (MAC / PCS / PMA layers)

Pay: $75.00 - $80.00 per hour

Work Location: Remote