Design Verification Engineer

Position would require the candidate to be a W2 employee of Donatech

• Develop verification plans based on requirements capture, decomposition, and traceability.

• Architect and implement advanced constrained random and directed verification environments (UVM/SystemVerilog).

• Create, develop, and maintain reusable verification components, testbenches, sequences, and functional coverage models.

• Perform ASIC/FPGA/SoPC verification using simulation, inspection, analysis, and hardware test methods.

• Conduct functional, code, and assertion coverage analysis and drive closure against verification goals.

• Apply best practice verification techniques including linting, CDC analysis, LEC, assertions, and regression automation.

• Collaborate with design teams to review architecture, interface specifications, and RTL implementation for testability and completeness.

• Generate DO 254 DAL A verification artifacts and support certification activities for Airborne Electronic Hardware (AEH).

• Participate in technical peer reviews and FAA SOI audits.

• Contribute to engineering bids, support RFIs/RFPs, and provide accurate estimation for verification scope and effort.

• Communicate effectively across engineering, program management, and customer teams.

• Mentor junior verification engineers and recommend workflow/tool enhancements for continuous improvement.

• May perform responsibilities associated with project engineering as required.

Qualifications You Must Have:

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field

• Experience developing testbenches and verification environments in SystemVerilog, VHDL, and/or Verilog.

• Hands-on experience with verification and simulation tools (e.g., Questasim, Vivado, Libero, Synplify Pro).

• Understanding of common digital interfaces (PCIe, DDR, Ethernet, I2C, ARINC429, CAN, etc.).

• Experience verifying timing behavior, devicelevel timing constraints, and clock domain crossings.

• Experience with scripting languages such as Python, Perl, Linux shell, or C/C++.

• Ability to work independently and collaboratively with globally distributed, crossfunctional engineering teams.

Qualifications We Prefer:

• Strong experience with UVM and constrained random verification methodology.

• Knowledge of DO 254 processes and verification-related design assurance activities.

• Familiarity with chip level verification best practices including functional coverage, code coverage, assertions, and LEC.

• Experience with video or networking technologies.

• Demonstrated ability to manage cost, schedule, and performance for verification activities.

• Basic risk management experience including identification, quantification, and mitigation planning.