Design Verification Engineer

Job highlights

• . B Tech /BE / ME/M Tech in Computer Science,Electronics / Electrical Engineering or related fields with 2 - 10 years of relevant hands-on experience
• Experience in Unit and SoC Verification,JTAG insertion

Key Responsibilities

• Work closely with design team to review the design spec and define/participate detailed testplan Strategy and verification plan
• Develop testbench at SOC level for complex ASIC System-On-Chips
• Develop and maintain verification environment in UVM
• Implementation verification including Scan, JTAG related logic.
• Develop and improve the verification flow and methodology
• Maintain regression and debug test failures with designers

Requirements :

• B. Tech /BE/ME/M Tech in Computer Science, Electronics/Electrical Engineering or related fields with 2 - 10 years of relevant hands-on experience.
• Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology)
• Experience in Unit and SoC Verification, JTAG insertion. Deep understanding of modern verification concepts.
• Good scripting skills in languages such as Perl, Tcl, or Python.
• Programming skills in System Verilog, C, C++
• Working knowledge of RTL coding in Verilog, Synthesis STA
• Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
• Excellent written and verbal communication skills.