Design Verification Engineer

• Working closely with the design architecture team and contributing to IP, performance and SoC related verification.
• Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.
• Writing configurable testbenches in SystemVerilog/UVM and testbench automation.
• Writing System verilog assertions and maintaining them.
• Writing functional coverage and overall functional and code coverage analysis.
• Working on ASIC power estimation and power-aware verification.
• Working on Gate Level Simulation and Emulators
• Automating tool flows and creation of result reports.

Desired Qualifications:

• 6-7 years of experience in functional verification of blocks/systems using SystemVerilog/UVM.
• Strong understanding of verification techniques including assertions, metric-driven and coverage-driven verification.
• Experience in developing full verification infrastructure from scratch.
• Experience with verification of systems which involve high-speed buses such as AXI4.
• Verification Experience on PCIe or DDR
• Working knowledge of Emulator based verification.
• Experience with gate level simulations and delay modeling.
• Experience with constraint random verification.
• Experience with writing functional coverage and overall code coverage analysis.
• Experience with coverage-driven verification methodology.
• Experience in writing and debugging System Verilog assertions.
• Strong experience in debugging RTL and testbenches.

Preferred Qualification:

• Prior experience in working with VIPs and verification environments which involve VIPs.
• Prior experience in verifying IPs/systems which include PCI-E/DDR (any) protocol.
• Experience with SoC level verification.
• Experience in using Continuous Integration tools such as Jenkins, Gitlab CI, Circle CI.
• Formal Verification techniques
• Emulation based verification
• Experience with scripting languages such as perl/python.