Design Verification Engineer

Job highlights

• Strong experience in test bench development using industry standard HVLs and methodologies such as SV / UVM

• Test bench development experience using SV / UVM

• Experience in IP level and SoC level verification

• SV and C / C++ based test bench experience is an added advantage

• Strong experience in test bench development using industry standard HVLs and methodologies such as SV/UVM.

• Strong digital design basics and debug skills.

• Defining the verification plan and test bench architecture from scratch.

• Test bench development experience using SV/UVM.

• Experience in IP level and SoC level verification.

• Constraint random verification, assertion based verification, quality checks such as Functional and Code coverage.

• Knowledge of niche protocols such as Ethernet, PCIe, CXL, DDR, USB, AMBA protocols is a plus.

• SV and C/C++ based test bench experience is an added advantage.

• Experience in industry standard simulation tools.

• Any scripting knowledge such as Perl, Python is a plus.