Design Verification Engineer

Location : Bay area (San Jose) CA ------- Onsite Duration : Long term Locals We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key Responsibilities End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

Understand vendor IP configurations and handle handshake with internal IP team

Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

10+ years of design verification experience

You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Experience handling vendors and integration of IP/VIP’s

UVM/System Verilog