Design Verification Engineer

Job highlights

• . Must have proven experience in developing HVL (System Verilog / UVM) based test environments,developing and implementing test plans,implementing and extracting verification metrics such as functional coverage and Code coverage

• Good communication skills,debug and problem-solving skills,mentoring teammates and should be self-motivated

• Experience in the verification of IP cores

• Experience in the verification of IP cores.

• Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.

• Experience on DDR Protocol is necessary. Understanding BIST would be an added advantage.

• Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable. Good communication skills, debug and problem-solving skills, mentoring teammates and should be self-motivated.

• Be a technical contributor in the Verification Tasks System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM.

• Creates deliverables which do not require close review or supervision by a Senior Technical Engineer.

• Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs.