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Design Verification Engineer - Contract

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Hybrid

Design Verification Engineer - Contract

Dotch Endeavours

Design Verification Engineer - Contract

Skills

PythonExpress

13 days ago

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Important information


Contract type:

Permanent

Salary:

₹750,000 – ₹1,750,000 / year

Location:

Bengaluru, Karnataka, India

Work mode:

Hybrid

Published on:

10 October 2026

What they need


Design Verification Engineer - Contract Opportunity

Employment Type: Contract Engineer
Joining Preference: Immediate to 30 days, subject to client requirements

Key Responsibilities

  • Develop and implement functional verification environments, including monitors, checkers, scoreboards and assertions.
  • Work with AMBA bus protocols and ARM CPU architectures.
  • Develop verification components using random stimulus and functional coverage methodologies.
  • Collaborate with cross-functional teams to integrate and troubleshoot verification components.
  • Use scripting languages such as Perl, Python, Shell or Makefile to automate verification processes.
  • Participate in debugging sessions and contribute to problem-solving activities.

Required Skills

  • Strong hands-on knowledge of SystemVerilog and UVM.
  • Practical experience in live design verification projects.
  • Knowledge of AMBA bus protocols and ARM CPU.
  • Experience developing functional verification environments, scoreboards, monitors, checkers and assertions.
  • Knowledge of random stimulus and functional coverage.
  • Familiarity with Unix, configuration management, bug-tracking and verification dashboarding tools.
  • Strong debugging, problem-solving and communication skills.

Good to Have

  • Experience with PCI Express and/or Ethernet bus protocols.
  • Scripting proficiency in Perl, Python, Shell or Makefile.
  • Experience working collaboratively with cross-functional engineering teams.

Who Should Apply?

  • Candidates with practical semiconductor Design Verification experience.
  • Professionals willing to take up a contract engineering engagement.
  • Candidates available to join immediately or within 30 days, preferably.
  • Applicants willing to attend client interviews and work at the confirmed project location.

How to Apply

Apply with your updated resume, highlighting your SystemVerilog/UVM experience, verification projects, AMBA protocol knowledge and notice period.

Shortlisted candidates will be contacted by zLanze for the next stage of screening and client interview coordination.

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