Design Verification Engineer (DV Engineer)

Design Verification Engineer (DV Engineer)

Location: Austin, TX / Bay Area, CA

Job Type: Contract / Full-Time

Job Overview

We are looking for an experienced Design Verification Engineer with strong expertise in SoC verification, SystemVerilog, and UVM . The ideal candidate should have hands-on experience verifying ARM-based processors and working with AMBA protocols .

Key Responsibilities

• Develop and execute verification environments for complex SoC designs .
• Develop reusable verification components using SystemVerilog (SV) and UVM .
• Verify ARM-based processor designs and related SoC functionality.
• Work with AMBA bus protocols and perform functional verification.
• Develop testbenches, test plans, assertions, and coverage models.
• Debug RTL, simulation failures, and functional issues.
• Collaborate with design, architecture, and validation teams to identify and resolve issues.
• Analyze verification results and drive coverage closure.

Required Skills & Qualifications

• Strong experience in SoC Design Verification .
• Hands-on experience with ARM processors/architecture .
• Strong proficiency in SystemVerilog (SV) .
• Expert-level experience with UVM .
• Good understanding of AMBA protocols such as AXI, AHB, or APB.
• Strong debugging and problem-solving skills .
• Experience with simulation and verification methodologies.

Preferred / Plus Skills

Experience with High-Speed I/O interfaces , such as:

• PCIe
• UCIe
• DDR
• MIPI
• Other high-speed interconnect and memory protocols