Design Verification Engineer – Gate-Level Simulation (GLS)

We are looking for a highly motivated Design Verification Engineer with strong expertise in Gate-Level Simulation (GLS) to execute and debug GLS activities across IP, Subsystem, and SoC levels. The ideal candidate should have hands-on experience in GLS setup, execution, timing validation, failure analysis, and closure. The role requires excellent debugging capabilities, collaboration with cross-functional teams, and the ability to adapt quickly to customer-specific flows and methodologies.

• Joining Location – Bangalore ,Hyderabad, coimbatore

Key Responsibilities

GLS Execution

• Setup, build, and execute Gate-Level Simulations across IP, Subsystem, and SoC levels.
• Support GLS activities across IPAR and MPAR validation environments.
• Run and analyze:
• Zero Delay Simulations
• SDF-Based Timing Simulations
• Power-Aware Simulations
• Drive simulation execution from environment setup through closure.

GLS Debug & Failure Analysis

• Debug and root-cause simulation failures including:
• Timing annotation issues
• Setup/Hold violations
• Clocking and reset issues
• X-Propagation issues
• RTL-to-Netlist mismatches
• Assertion failures
• Coverage failures
• Test failures
• Analyze waveform dumps and identify underlying design or implementation issues.
• Work closely with Design, STA, Physical Design, and Verification teams to resolve GLS failures.

Verification & Validation

• Perform failure triaging and closure of GLS issues.
• Support assertion-based verification and coverage analysis.
• Contribute to functional and timing signoff through comprehensive debug and verification activities.
• Ensure RTL and netlist behavioral consistency through detailed analysis.

Collaboration

• Work closely with cross-functional teams to drive issue resolution.
• Communicate debug findings and provide timely status updates.
• Quickly adapt to customer-specific tools, methodologies, and execution environments.
• Actively contribute as a team player in a fast-paced project environment.

Required Technical Skills

Gate-Level Simulation

• 4+ years (or 7+ years for senior roles) of hands-on experience in GLS.
• Strong understanding of:
• GLS methodology
• SDF annotation
• Timing validation
• Power-aware simulation
• RTL-to-Gate correlation
• Netlist-based verification

Debug Expertise

Strong experience in debugging:

• Timing annotation failures
• Setup/Hold violations
• Clock domain issues
• X-propagation problems
• Assertion failures
• Coverage failures
• Test failures
• RTL vs Netlist behavioral divergences

Tools & Languages

• SystemVerilog
• UVM
• SVA (SystemVerilog Assertions)
• VCS / Xcelium / Questa
• Verdi / DVE / SimVision
• Linux/Unix
• Perl / Python / Shell Scripting

Preferred Qualifications

• Experience working on large-scale SoC validation programs.
• Exposure to synthesis, STA, DFT, and Physical Design flows.
• Strong understanding of SoC architecture and subsystem interactions.
• Experience with protocol verification, assertion development, and coverage closure.
• Ability to independently own debug activities and drive issues to closure.

Desired Candidate Profile

• Strong analytical and debugging skills.
• Passion for solving complex gate-level and timing-related issues.
• Self-driven with the ability to work independently.
• Excellent communication and collaboration skills.
• Proven ability to work effectively within cross-functional engineering teams.
• Adaptable and quick to learn new methodologies and validation environments.
• Porting functional test cases from SoC/block level for GLS Pattern generation,
• post silicon debug, silicon characterization Team work skills to work with
• design, verification, post silicon teams.
• Expertise in functional domain PCI Express, MAC, WiFi baseband/radio will be
• added advantage
• Debug non-timing and timing Embedded RISC/ARM/DSP processor architecture based on verification is mandatory RTL
• design, chip/block level DV with vera/systemVerilog is added advantage.