Design Verification Engineer (Internal IP)

• We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready
• This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack
• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems)
• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks
• Debug complex datapath and protocol issues in RTL and testbench environments
• Work closely with architects and designers to validate functionality and design intent
• Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage
• Contribute to reusable DV infrastructure, coverage models, and methodology improvements

Benefits

• Competitive Salary and Equity - We offer a competitive salary and equity package that aligns with industry standards
• Benefits - Your wellbeing is important to us. We offer unlimited PTO, life insurance, and a 401(k)
• Full Insurance Coverage - Our insurance includes full medical, dental, and vision with 100% of premium covered- Strong debugging and problem-solving skills for complex digital designs
• Solid knowledge of computer architecture and digital design fundamentals
• Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics
• Proficiency with UVM and SystemVerilog
• Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows
• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols
• Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques