Design Verification Engineer - IP/Subsystem, Low Power

Job highlights

• The ideal candidate should be proficient in System Verilog,UVM,and Low Power Verification (UPF),along with exposure to Formal Verification and ARM-based protocols
• Required Skills and Experience: Hands-on experience in IP / Block or Subsystem level verification. Strong proficiency in System Verilog and UVM.
• Experience in Low Power Verification using UPF.

Location : Bangalore

Experience: 5+ Years

Job Description:
We are looking for a Design Verification (DV) Engineer with strong hands-on experience in IP/Block or Subsystem level verification. The ideal candidate should be proficient in System Verilog, UVM, and Low Power Verification (UPF), along with exposure to Formal Verification and ARM-based protocols.

Key Responsibilities:
Perform IP/Block and Subsystem level verification using System Verilog and UVM methodology.
Develop and maintain test plans, test benches, and coverage models for verification.
Conduct Low Power Verification using UPF (Unified Power Format).
Analyze and achieve code coverage and functional coverage goals.
Work on Formal Verification to ensure design correctness.
Verify designs implementing ARM protocols (AXI, AHB).
Develop and maintain automation scripts using Perl or Python to improve verification efficiency.

Required Skills and Experience:
Hands-on experience in IP/Block or Subsystem level verification.
Strong proficiency in System Verilog and UVM.
Experience in Low Power Verification using UPF.
Knowledge of Formal Verification techniques and tools.
Familiarity with ARM protocols - AXI, AHB.
Scripting experience in Perl, Python, or similar languages.
Excellent debugging, problem-solving, and analytical skills.