Design Verification Engineer / Lead

Design Verification Engineer / Lead

📍 Location: Hyderabad, India – Onsite

💼 Experience: 8–15 Years

🎓 Qualification: BE / ME

🔍 Key Skills Required:

✅ SystemVerilog & UVM

✅ SoC-Level & Subsystem Verification

✅ IP Integration & Interconnect Verification

✅ AXI, AHB & APB Protocols

✅ PCIe, Ethernet, USB, DDR, CXL, or similar high-speed interfaces

✅ Assertions, Constrained-Random Testing & Functional Coverage

✅ Simulation Debugging & Coverage Closure

• 📩 Interested candidates: Share your updated resume at [email protected]