Design Verification Engineer – SoC / Digital Verification

Key Responsibilities

• Develop and execute verification strategies and comprehensive test plans for SoC/Digital designs.
• Create reusable and robust test cases using SystemVerilog and UVM.
• Perform protocol-level verification for PCIe and/or UCIe interfaces.
• Develop test scenarios to validate design functionality, corner cases, and protocol compliance.
• Define verification plans, coverage goals, and regression strategies.
• Debug simulation failures, identify root causes, and resolve complex verification issues.
• Analyze functional coverage and drive verification closure.
• Collaborate with design and verification teams to ensure quality and timely delivery.

Mandatory Technical Skills

• Experience: 6+ years of relevant experience in SoC/Digital Design Verification.
• SystemVerilog (SV): Strong hands-on programming and verification experience.
• UVM: Solid experience developing and maintaining UVM-based testbenches.
• PCIe and/or UCIe: Practical experience in protocol verification.
• SoC Architecture: Strong understanding of SoC design and verification methodologies.
• C/C++: Good programming and debugging skills.
• Test Development: Experience developing comprehensive, reusable test cases and test scenarios.
• Test Planning: Ability to define verification strategies, test plans, coverage goals, and execution plans.
• Debugging: Strong failure analysis, root-cause identification, and issue resolution skills.
• Functional Verification: Good understanding of simulation, functional coverage, regression testing, and verification closure.

Candidate Requirements

• Strong hands-on experience in SV/UVM-based SoC verification.
• Meaningful practical exposure to PCIe and/or UCIe protocols.
• Proven experience in testbench development, test execution, debugging, and coverage analysis.
• Ability to independently analyze complex failures and drive issues toward resolution.
• Strong problem-solving and analytical skills.