Design Verification (GLS/Functional Ver) - Hyd Mirafra Technologies

Mirafra Technologies is Hiring!

Location: Hyderabad

Experience: 3 to 8 Years

Send your resume to: [email protected]

Role: Design Verification Engineer

We are looking for experienced Functional Verification Engineers with strong expertise in SystemVerilog/UVM to develop and maintain block-level and IP-level verification environments.
The ideal candidate is proactive, self-driven, and capable of handling deliverables independently.

Key Responsibilities:

Develop and maintain block-level testbenches using SystemVerilog/UVM
Create and execute verification plans (V-Plan), run regressions, and drive coverage closure
Work on testbenches with real number modeling
Perform netlist and gate-level simulations

Qualifications & Experience:

Bachelors degree or higher in Electronics or related field
510 years of experience in Functional Verification
Strong hands-on experience in SystemVerilog/UVM
Experience in block/IP-level verification
Subsystem or SoC-level experience will be an added advantage
Excellent communication and ability to work independently

If this sounds like you, we’d love to hear from you!

Send your resume to: [email protected]