Design Verification Manager

Key Responsibilities

• Lead and manage the Design Verification team and projects.
• Define DV strategy, methodology, test plans, and verification schedules.
• Drive functional, system-level, and regression verification to achieve coverage targets.
• Review testbench, SystemVerilog/UVM, assertions, and coverage implementation.
• Work closely with RTL, architecture, emulation/FPGA, and software teams to resolve issues.
• Mentor engineers and drive continuous improvement of DV processes.

Requirements

• 10+ years of experience in ASIC/SoC Design Verification, with proven team/project leadership experience.
• Strong knowledge of SystemVerilog and UVM.
• Experience with functional coverage, assertions, and verification methodologies.
• Strong debugging, problem-solving, communication, and people-management skills.