Mirafra Software Technologies
Design Verification: PAGLS
Skills
1 month ago
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Important information
Location:
Karnataka, India
Work mode:
Onsite
Published on:
25 September 2026
What they need
Design Verification: PAGLS
Location: Bangalore
Job Description:
- Subsystem/SoC level digital verification using constrained-random coverage methodologies at both RTL and Gate Level with UPF
- SOC,GLS and PAGLS
- Experience with Power aware(UPF) verification at RTL And GLS simulations
- Experience in writing Test Plans independently
- Experience in writing/updating Verification Testbench
- Experience with debugging RTL & Gate level simulations
- Experience with Functional Coverage &Code Coverage
- Experience with Scripting in perl, python, tcl
- Experience in planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage
- Should have been involved in leading a chip DV effort
- Should have been self-driven and quick learner
Experience (years) : 4-12 years
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
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