DFT Architect for Data Center ASIC products

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. Key Responsibilities

• Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios.
• End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches
• Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation
• Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications
• Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements
• Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement
• Location: Hsinchu, Taipei, Singapore, USA

Main Requirements and Qualifications

• Proven DFT Expertise: Extensive engineering experience across complete DFT lifecycle, including pre-silicon architecture definition through post-silicon validation and production ramp
• Architecture Leadership: Demonstrated success in creating and implementing complex multi-die DFT architectures for advanced semiconductor products
• Comprehensive DFT Implementation: Hands-on experience with Scan and Scan Compression techniques at both IP and SoC levels, with deep understanding of integration challenges
• DFT Tool Proficiency: Strong command of industry-standard DFT tools and ATPG methodologies including Stuck-At, At-Speed, and Path-Delay fault models with scan compression techniques
• Memory Test Expertise: In-depth knowledge of MBIST architecture, implementation, and optimization strategies
• High-Speed Interface Knowledge: Experience in PHY design, high-speed IO protocols, digital communication interfaces, and functional test development
• Advanced DFT Technologies: Knowledge of Tessent Streaming Scan Network (SSN); hands-on implementation experience highly preferred
• Silicon Debug Proficiency: Practical experience with post-silicon debugging techniques and lab equipment including oscilloscopes, logic analyzers, and ATE platforms
• Digital Design Foundation: Solid understanding of Verilog RTL, synthesis optimization, physical implementation flows, and Static Timing Analysis
• Verification Methodology: Strong grasp of modern verification approaches and best practices
• FPGA Design Experience (Preferred): Familiarity with FPGA logic design, synthesis workflows, and implementation methodologies
• Collaborative Team Player: Excellent communication skills with proven ability to work effectively in cross-functional team environments and drive consensus across diverse stakeholder groups
• Education: M.S. or Ph D. in Electrical Engineering, Computer Engineering, or related field.