Dft Design Engineer

Job Description: DFT Engineer (48 Years Experience)

Position: DFT Engineer

Experience: 48 Years

Location: Bangalore / Hyderabad

Job Summary

We are looking for an experienced DFT Engineer with 4–8 years of hands-on expertise in Design for Test (DFT) implementation, verification, and ATPG for complex SoC designs. The ideal candidate should have strong knowledge of scan architecture, MBIST, JTAG, compression techniques, and test pattern generation, along with experience working closely with RTL, physical design, and validation teams.

Key Responsibilities

• Define and implement DFT architecture for complex SoC/IP designs.
• Insert and verify Scan, MBIST, Boundary Scan (JTAG), and test compression logic.
• Perform DFT rule checks and ensure testability requirements are met.
• Generate ATPG patterns for stuck-at, transition, bridge, and path delay faults.
• Analyze fault coverage and debug pattern generation issues.
• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams to resolve DFT-related issues.
• Support silicon bring-up, manufacturing test, and yield improvement activities.
• Develop and maintain DFT scripts using Tcl, Perl, or Python.
• Participate in design reviews and contribute to DFT methodology improvements.
• Ensure compliance with DFT sign-off requirements and project timelines.

Required Skills

• Strong understanding of Scan Architecture and Scan Insertion.
• Hands-on experience with ATPG and fault coverage analysis.
• Experience with MBIST implementation and memory repair concepts.
• Knowledge of IEEE 1149.1/1149.6 (JTAG/Boundary Scan).
• Familiarity with test compression techniques such as EDT or similar.
• Experience in DFT verification using simulation and formal methodologies.
• Good understanding of digital design, RTL, and ASIC design flow.
• Strong debugging and problem-solving skills.
• Proficiency in scripting using Tcl, Perl, Python, or Shell.