DFT (Design for Testability) Engineer

• Job Title: Senior / Manager - DFT (Design for Testability) Engineer
• Location: Bangalore, Karnataka, India (Work from Office / Hybrid / Remote flexibility based on project requirements)
• Job Type: Full Time
• Experience Required: 3 – 15 Years

About the Company

We are recruiting on behalf of a trusted and rapidly growing leader in the semiconductor market (established in 2017 and headquartered in India), delivering innovative chip design and verification solutions to major global clients.

Role Overview

We are looking for experienced and hands-on Core DFT Engineers (Senior/Manager level) to join our growing engineering team in Bangalore. The ideal candidate will have a clear, practical understanding of advanced DFT concepts, strong debugging skills, and hands-on experience with industry-standard EDA tools.

Key Responsibilities & Mandatory Skills

• Core Expertise: Hands-on experience in at least one of the following areas:
• ATPG (Automatic Test Pattern Generation) & pattern generation/simulations (Mandatory)
• GLS (Gate Level Simulation) — including zero delay and SDF Timing Simulations (Mandatory)
• Scan Insertion & Scan Architecture
• MBIST (Memory Built-In Self-Test) insertion and simulations
• BSCAN / IJTAG / Boundary Scan
• EDA Tools Proficiency: Experience using industry-standard tools from Cadence, Siemens (Tessent), or Synopsys.
• Debugging & Verification: Strong debugging skills using the GUI mode of simulators such as VCS, NCSim, or Xcelium.
• Fault Models & Coverage: Working knowledge of fault models including stuck-at, Transition Delay Faults (TDF), and IDDQ, along with experience in scan test coverage improvement techniques.
• SoC Level Experience: Experience in SoC-level DFT, OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes, and post-silicon bring-up and/or production activities (including tester debug using shmoo plots and graphs).
• Timing Constraints: Experience in providing test mode timing constraints to STA and Physical Design (PD) teams.
• Leadership & Communication: Excellent communication and collaboration skills to interact with cross-functional teams and clients, along with the ability to mentor junior DFT engineers.

Good-to-Have Skills

• Automation and scripting experience
• Exposure to cloud tools and AI-driven design environments

Interview & Hiring Process

• Interview Rounds: 2 to 3 rounds of virtual interviews.
• Work Schedule: Regular work hours (Work from Office with hybrid/remote flexibility depending on project needs).

Pay: ₹1,500,000.00 - ₹5,000,000.00 per month

Benefits:

• Flexible schedule
• Health insurance
• Life insurance
• Paid sick time
• Provident Fund
• Work from home

Application Question(s):

• Do you have hands-on experience in the DFT (Design for Testability) segment, specifically with ATPG and Gate Level Simulation (GLS)?
• How many years of hands-on experience do you have in the DFT segment?
• Are you currently based in Bangalore or open to working from the office in Bangalore (with hybrid/remote flexibility based on projects)?

Work Location: In person