DFT Engineer

Well versed in Verilog/VHDL RTL coding, experienced in using Mentor DFT, Cadence and Synopsys EDA tools. Hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Must have worked on few SoC DFT effort at least, from start to end. Must be proactive, collaborative and detail-oriented capable of exercising independent judgment. Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug.