DFT Engineer

Responsibilities:

-Execute Scan insertion, Scan DRC check and debug. review DRC reports, debug and resolve

DRCs

-Tmax pattern generation, Optimize ATPG patterns and improve Fault coverage, check and

debug ATPG DRCs

-Knowledge of Codec/EDT architecture, OCC working in different modes, DFT mode clockings

• to debug complex scan issues indepedently/with minimum supervision

-Verify ATPG tests in Zero delay and SDF annotated simulations

-Debug simulation failures in VCS, Verdi and other simulators

-Work on pattern porting, contribute to DFT methodology and flow automation

-Post silicon validation and debug; Ablity to support ATE silicon debugs

Requirements:

-B.Tech / M.Tech (preferred) with 8-15 years of experience in DFT

-Strong knowledge of DFT architecture, methodologies and structural debug concepts : JTAG,

IEEE1500, Scan tests debug

-Experience in handling DFT of the large multi multimillion gate multi clock domain SoCs

-Hands on experience in SCAN, ATPG and JTAG implementation at block and chip level

-Knowledge of Verilog RTL and hands on experience in using simulators and waveform

debugging tools such as VCS and Verdi

-Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC

-Experience in post silicon debug

-Knowledge of Python, , Shell scripting, Makefiles, TCL

-Excellent problem solving skills and highly self-motivated