DFT Engineer

DFT Engineer

Location: Santa Clara, CA — Hybrid
Openings: 9
Contract Type: Contract
Compensation: $70/hour, depending on engagement structure

About the Role

We are seeking experienced DFT Engineers to support semiconductor design and test programs. The ideal candidate will have strong hands-on experience with Design-for-Test (DFT), ATPG, scan-based testing, and memory test methodologies for ASIC or SoC designs.

Key Responsibilities

Develop, implement, and support DFT solutions for ASIC and SoC designs.

Generate, analyze, debug, and optimize ATPG patterns.

Work with scan insertion, scan chains, controllability, and observability concepts.

Support MBIST implementation, memory test architectures, and diagnostics.

Contribute to I/O test methodologies for interface and pin-level validation.

Support clock DFT and clock-related test and verification activities.

Review RTL and digital design requirements related to DFT implementation.

Use industry-standard DFT and ATPG EDA tools for implementation, analysis, and debugging.

Collaborate with design, verification, physical design, and test teams to resolve technical issues.

Analyze test results, identify failures, and recommend solutions.

Work effectively in a fast-paced semiconductor development environment.

Required Qualifications

5+ years of hands-on experience in DFT and ATPG for ASIC or SoC designs.

Strong understanding of DFT fundamentals, including controllability, observability, and scan-based testing.

Practical experience with ATPG pattern generation, analysis, and debug.

Experience with MBIST and memory test methodologies.

Knowledge of I/O test methodologies and pin-level validation.

Understanding of clock DFT and clock verification concepts.

Strong knowledge of digital design and RTL fundamentals.

Experience working with industry-standard DFT/ATPG EDA tools.

Strong analytical, troubleshooting, and problem-solving skills.

Good written and verbal communication skills.

Work Arrangement

This is a hybrid position based in Santa Clara, California. Candidates should be able to work effectively in a collaborative, high-performance semiconductor engineering environment.

Equal Opportunity: We consider qualified candidates based on their skills, experience, and qualifications.

Pay: $60.00 - $70.00 per hour

Expected hours: 42.0 per week

Work Location: Hybrid remote in Santa Clara, CA 95056