DFT Engineer

Job Title: DFT Engineer

City: Santa Clara

State/Province: California

Posting Start Date: 10/14/26

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Role Purpose
The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client

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Experience :- 6 to 8 yrs

We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality.

Key Responsibilities

Create and execute test plans for DFX features including Scan, MBIST, SSN, EDT, IJTAG, and JTAG.

Verify DFX implementations at IP, subsystem, and SoC levels.

Develop SystemVerilog/UVM based verification environments and test benches.

Debug regression failures and identify root causes related to design or verification.

Generate and validate Scan/ATPG patterns for production testing.

Collaborate with cross-functional teams including Design, Architecture, Physical Design, Validation, and ATE teams.

Automate DFX flows using scripting languages and improve overall test methodologies.

Contribute to DFX architecture planning and implementation for next-generation SoCs.

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Required Technical Skills

DFX / DFT

Scan Insertion & Compression

ATPG Pattern Generation & Debug

MBIST / LBIST

JTAG, IEEE 1500, IEEE 1687 (IJTAG)

SSN (Streaming Scan Network)

EDA Tools

Siemens Tessent Suite (TestKompress, MBIST, SSN, IJTAG, EDT)

Synopsys Fusion Compiler

Synopsys Design Compiler

SpyGlass

RTL and Gate-Level Simulation Tools

Verification

SystemVerilog

UVM

Assertions (SVA)

Functional and Code Coverage

SoC/IP Verification

Python/Perl, TCL/Shell Scripting

Preferred Qualifications

Experience in end-to-end DFX flow development.

Strong understanding of ASIC/SoC design flow from RTL to silicon.

Exposure to high-speed interfaces such as PCIe, DDR, Ethernet, USB, CXL, UCIe, or SerDes is a plus.

Educational Qualification

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Computer Engineering, or related fields.

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Mandatory Skills: VLSI Design For Testability - DFT .
Experience: 5-8 Years .
The expected compensation for this role ranges from $60,000 to $148,500 .
Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.
Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.
Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.
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