DFT Engineer

We are seeking a highly skilled Staff Engineer - Design to lead ASIC design implementation activities from architectural understanding through RTL-to-GDS execution and timing signoff. The successful candidate will drive design implementation excellence, support advanced technology nodes, and contribute to methodology improvements for successful tape-outs.

Responsibilities:

• ASIC Design Implementation Lead ASIC design implementation activities from RTL synthesis to timing signoff and tape-out.
• Develop and improve RTL-to-GDS implementation flows and methodologies.
• Understand architectural and micro-architectural design intent to ensure successful implementation.
• Optimize RTL structures for efficient synthesis and physical design convergence.
• Develop, review, and validate timing constraints with designers and architects.
• Drive Design-for-Test (DFT) implementation, including scan insertion, compression, LOC/LOS, RAM BIST, and advanced DFT optimization techniques.
• Support low-power design methodologies, including power-aware optimization, leakage reduction, and dynamic power control techniques.
• Provide technical leadership, mentoring, and guidance to team members in resolving complex implementation challenges.
• Contribute to innovation through patents, technical publications, and proprietary design methodologies.
• Benchmark and drive best-in-class ASIC implementation methodologies and processes. Documentation & Process Compliance Document implementation methodologies, design considerations, challenges, and solutions using company standards.
• Complete design audits, reviews, and compliance checklists in accordance with corporate Design Control Procedures (DCP).
• Maintain accurate records of issues, resolutions, and design reviews within PEPS, JIRA, or other project management systems.

Requirements

• Bachelor's or Master's Degree in Electrical/Electronics Engineering or a related discipline.
• 8 - 12 years of hands-on experience in ASIC Physical Design or Design Implementation.
• Strong expertise in: Cadence Genus or Synopsys Design Compiler, Cadence Tempus or Synopsys PrimeTime
• Proven experience in synthesis, timing closure, and timing signoff.
• Strong understanding of ASIC implementation methodologies, timing constraints, and optimization techniques.
• Excellent analytical, troubleshooting, and problem-solving skills.
• Strong communication and technical leadership capabilities.

Pay: Up to RM17,000.00 per month

Benefits:

• Cell phone reimbursement
• Dental insurance
• Free parking
• Maternity leave
• Opportunities for promotion
• Parental leave
• Professional development
• Vision insurance

Ability to commute/relocate:

• Bayan Lepas: Reliably commute or planning to relocate before starting work (Required)

Application Question(s):

• How many years have you worked in ASIC chip design or implementation?
• Which synthesis tool and which timing (STA) tool do you use hands on? One of Genus / Design Compiler AND one of Tempus / PrimeTime
• Walk me through your last tape-out. Which stages did you own, from design code to the final file sent to the factory
• What DFT work have you done? How do you balance test coverage against schedule and chip performance?
• How do you write timing constraints from a design spec, and how do you sign off timing for tape out?
• What low-power techniques have you implemented, and how did you measure the savings?
• How do you set up and tune synthesis to hit timing, area and power? What do you check in the results?
• Bachelor's or Master's in Electrical or Electronics Engineering?
• Are you available immediately or notice period 1-2 months?
• Are you authorized to work in Malaysia?

Location:

• Bayan Lepas (Preferred)

Work Location: In person