DFT Engineer

Lead DFT architecture and test strategy definition for advanced SoCs, ensuring high-quality manufacturing testability and diagnosis readiness.

Job Description - Grade Specific

Key Responsibilities

• Define SoC DFT architecture.
• Establish ATPG, scan, MBIST, LBIST strategies.
• Drive test coverage objectives.
• Define compression and diagnosis methodologies.
• Work with RTL, Verification, and Physical Design teams.
• Review DFT signoff requirements.
• Interface with customer test and manufacturing organizations.

Must Have

• 12+ years of DFT experience.
• Multiple successful SoC tapeouts.
• Good Knowledge on RISC and ARM SoC DFT strategy for sub-systems and top level
• Expertise in scan insertion and ATPG.
• Strong understanding of MBIST/LBIST.
• Experience with Tessent and/or Synopsys DFT tools.
• Knowledge of test compression and diagnosis.
• Understanding of JTAG and IEEE 1500/1687.

Good to Have

• Safety DFT.
• Automotive test methodologies.
• Silicon bring-up support experience.
• Yield learning and diagnosis.
• Chiplet test architecture.
• Advanced node test challenges.