K
Kandou AI
DFT - Full Time
1 month ago
Share this opportunity
Share this opportunity to other talents of your network:
✓ Offer them a visibility boost with clients.
✓ Help your contacts find their next job.
Important information
Contract type:
Permanent
Location:
Telangana, India
Work mode:
Onsite
Published on:
11 September 2026
What they need
Key Responsibilities:
- Lead DFT activity for the next generation products
- Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth SerDes, DDR, PCIe designs
- Closely working with Physical implementation team to define timing constraints in test modes and helping to converge for successful tapeout
- Good understanding of ATE, knowledge of probe and final test bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development
- Define the test plan by closely working with the design teams and drive the pattern development of functional/structural tests for final/wafer test program
- Closely working with the cross functional teams to bring up device qualification solution for HTOL
- Drive lab bench silicon debug to understand ATE bring up issues
Skills:
- Excellent communication skills, and strong team player with can do type of attitude
- Mentoring the team members
- Excellent debugging skills
- Process oriented to drive automation to help increase productivity and quality
Qualifications:
- 12+ years of DFT experience including architecture specification, implementation, test pattern development, and simulation
- Proven track record of delivering DFT solution to complex designs
- Experience working with IJTAG methodologies, understanding device functionality
- Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
- Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
- Strong debug capabilities in simulating patterns with timing
- Experience in defining test mode constraints and analyzing the timing reports
- Experience with industry standard EDA tools for DFT, timing, and simulation
- Good knowledge of System Verilog
- Experience with chiplet based designs is a plus
Education:
- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering or similar fields (equivalent or higher)
Other offers great for you!
These companies are also looking for great profiles
C
Celad
Développeur Full Stack Java - Angular H/F
Permanent contract
06560 Valbonne, France
Onsite
Skills
Fullstack Development
14 hours ago
Quick apply
O
Okara
Développeur full stack Typescript (H/F)
400-500
Freelance
Lille, France
Hybrid
Skills
VueNodeNuxt
13 hours ago
Quick apply
C
Creme de la creme
Architecte senior - Knowledge Graph (Full remote)
Freelance
Remote
Skills
Data EngineeringNeo4jKnowledge GraphGraphRAGAgentic AILocal LLMs
5 hours ago
Quick apply