DFT Lead

About the Company - Leading Semiconductor Manufacturing Company (Full time)

Experience: 8 - 20 years.

About the Role

We are looking for an experienced Lead DFT Engineer to own and drive end-to-end Design for Testability (DFT) strategies for our next-generation, high-performance SoCs. In this role, you will lead the execution of advanced test architectures, collaborate closely with cross-functional chip design teams, and ensure high test quality and silicon yield.

Responsibilities

• Architect and lead DFT strategies: Define, implement, and drive comprehensive DFT architectures—including Scan/ATPG, MBIST, Boundary Scan.
• Drive technical execution: Oversee the implementation of test compression, fault modeling (stuck-at, transition, cell-aware), memory self-tests, and high-speed I/O testing to maximize test coverage and minimize ATE test costs.
• Lead cross-functional integration: Collaborate closely with architecture, RTL synthesis, physical design, and timing closure teams to integrate DFT logic without compromising power, performance, and area (PPA).
• Manage silicon bring-up and debug: Direct ATE vector generation, failure analysis, and hands-on silicon bring-up in the lab to debug test pattern issues and rapidly resolve yield limiters.
• Mentor and guide engineering teams: Provide technical leadership, establish methodology best practices, delegate tasks, and guide junior to mid-level DFT engineers across the project lifecycle.

Required Skills

• Technical Skills: Deep hands-on proficiency with industry-standard DFT tools (Synopsys TestMAX / Cadence Modus / Siemens Tessent).
• Expertise in Scan, Compression, ATPG, MBIST, IJTAG (IEEE 1687), and Boundary Scan architecture.
• Experience with static timing analysis (STA) constraint development and timing closure for DFT modes.
• Solid scripting skills in Tcl, Python, or Perl for automation.
• Proven experience in silicon bring-up, ATE pattern generation, and failure diagnosis.