DFT Timing Lead

Job Summary

SMTS/MTS Silicon Design Engineer

The Role: As a key member of the S3 SoC DFT Team, the successful candidate will play a significant role in ensuring the quality of next generation AMD SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.

Whether you re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we ll advance your career.

Responsibilities

• Develop full chip DFT Synthesis and DFT STA constraints.
• STA constraint development of DFT modes (ScanShift, Atspeed, MBIST)
• Set up DFT timing constraints, defining the overall SOC Test STA methodology.
• Working with the Design team to clean-up all the DFT related constraint issues
• Closely work with physical design team to generate and validate timing constraints
• Developing, improving and maintaining automation scripts as necessary

Preferred Experience

• Experience in DFT architecture for complex chips
• Exposure to Static timing analysis Timing closure is required.
• Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA).
• Experience in SOC timing closure in DFT modes and sign-off
• Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
• Excellent hands-on debug skills and scripting skills are critical.

Qualifications

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8 to 15 years of DFT Experience

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