DFT Verification Engineer

Role: DFT Verification Engineer

Fulltime role with L&T Technology Services (LTTS)

Location: Santa Clara, CA, California – Onsite

Summary:

DFT Verification Engineers with Strong RTL and gate-level debug skills using Verilog/SystemVerilog, simulation, and waveform analysis.

Key Responsibilities

• Verify and debug complex scan and DFT architectures from pre-silicon development through silicon bring-up.
• Integrate, validate, and debug Tessent JTAG and Tessent SSN solutions on large SoC designs.
• Develop verification plans and environments for test-access, test modes, clocks, resets, and pattern execution.
• Debug scan debug/DFD, clocking, Jtag and 1838 related failures
• Support post-silicon scan bring-up, failure analysis, and root-cause identification.
• Develop scripts and automation to improve verification, debug, and failure-triage efficiency.
• Experience with Jtag Tap and DFD is a preferred skill.
• Strong RTL and gate-level debug skills using Verilog/SystemVerilog, simulation, and waveform analysis.