Digital Circuit Design Engineer

Experience : 1 to 3 Years

Location : Hyderabad

Mode Of Interview : In-Person

Job Title : Digital Circuit Design Engineer

Experience: 1yrs to 3yrs.

? Hands-on experience in developing/understanding building block schematics, memory

schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.

? Experience in deciphering circuit behavior from schematics.

? Familiarity with circuit characterization, timing libraries - files and formats, timing arcs

? Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit

delay, and path delay simulations.

? Familiarity with static timing analysis

? Hands-on experience in Gate level simulations with SDF back annotation.

? Debug SDF annotation issues and ensure good annotation coverage.

? Hands-on experience with latch based designs and their timing requirements.

? Debugging Gate level simulation failures and root causing the failures to actual circuits.

Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.

? Hands-on knowhow of System Verilog Assertions to specify expected design behavior

? Familiarity with UVM is a plus

? Strong communication skills, with the ability to convey complex technical concepts to other

design peers in verbal and written form.

? Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor

level - as appli

Qualifications: B.Tech/MTech