A
Astera Labs
Digital Design Engineer
Skills
PythonExpress
1 month ago
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Important information
Location:
San Francisco, CA, USA
Work mode:
Onsite
Published on:
1 October 2026
What they need
Who you are
- The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred
- +3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately
- Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc
- Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc
- Block level ownership from architecture to GDS
- Experience with Synopsys and/or Cadence digital design tools/flows
- Knowledge of design for test (DFT)
- Familiarity with UVM based design verification
- Silicon bring-up and debug experience
- Small-geometry CMOS (≤28nm) design
- Scripting with Python or other equivalent programming languages
- Development/support for PCIe or Ethernet Switch products
What the job involves
- We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers
Benefits
- Flexible time off in the US
- Parental leave
- Competitive medical, dental and vision plans
- 401K
- Retirement and pension plans
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