Digital Design Engineer (Senior)

R&D jobsAntwerp, BelgiumMaster or above

We are looking for a senior-level Digital Design Engineer with 5+ years of relevant experience to be responsible for the study, design and verification of the digital circuits of advanced CMOS image sensors. Key Responsibilities

• Define and study digital specifications for advanced CMOS image sensors, including area and power estimations.
• Support the technical lead in defining the sensor architecture.
• Design and implement digital circuits in RTL (VHDL), keeping performance, power and area optimizations in mind.
• Develop verification environments, testbenches, checkers and test scenarios in UVM (SystemVerilog), run regressions and debug results.
• Use constrained-random verification, define coverage metrics and drive coverage closure.
• Work together with different teams and communicate efficiently to successfully complete the project.
• Participate in design/architecture reviews and risk assessments.
• Write clear and comprehensive technical documentation.
• Give technical support including interaction with customers and/or suppliers.
• Lead, attend and present at project/review meetings worldwide.
• Contribute to methodology and flow improvements in design, verification and overall development efficiency.
• Mentor and coach junior team members with technical expertise and best practices.
• Contribute to conference publications, technical papers and the company's patent portfolio

Position Responsibilities

We are looking for a senior-level Digital Design Engineer with 5+ years of relevant experience to be responsible for the study, design and verification of the digital circuits of advanced CMOS image sensors. Key Responsibilities

• Define and study digital specifications for advanced CMOS image sensors, including area and power estimations.
• Support the technical lead in defining the sensor architecture.
• Design and implement digital circuits in RTL (VHDL), keeping performance, power and area optimizations in mind.
• Develop verification environments, testbenches, checkers and test scenarios in UVM (SystemVerilog), run regressions and debug results.
• Use constrained-random verification, define coverage metrics and drive coverage closure.
• Work together with different teams and communicate efficiently to successfully complete the project.
• Participate in design/architecture reviews and risk assessments.
• Write clear and comprehensive technical documentation.
• Give technical support including interaction with customers and/or suppliers.
• Lead, attend and present at project/review meetings worldwide.
• Contribute to methodology and flow improvements in design, verification and overall development efficiency.
• Mentor and coach junior team members with technical expertise and best practices.
• Contribute to conference publications, technical papers and the company's patent portfolio<

Position Qualifications

• Bachelor’s degree or above in microelectronics or related fields.
• 5+ years of relevant experience in digital IC design and verification
• Strong expertise in digital architecture, RTL design (VHDL/Verilog) and functional verification (SystemVerilog/UVM).
• Hands-on experience with chip-level mixed signal verification.
• Good understanding of synthesis, place & route and timing analysis to support digital backend engineers.
• Can comfortably (learn to) use relevant scripting and/or programming languages.
• Solid understanding of the complete IC development flow.
• Able to combine an organized and methodical design philosophy with a sense for creativity and innovation.
• Strong analytical, problem-solving and debugging skills.
• Can integrate and work easily in a small and dynamic team in an international environment.
• Fluent in English, both spoken and written.
• Strong plus:
• Experience in mixed-signal ASIC development
• Experience with CMOS image sensor architectures and/or image-processing pipelines.
• Hands-on experience executing the digital backend flow from RTL to GDS.
• Experience leading digital projects<

Send resume to [email protected]