Digital IC Design Engineer_2026

Job Overview

Responsible for developing micro-architectures and RTL designs for complex digital IPs and SoCs. The role covers key stages of the ASIC design flow, including RTL development, synthesis, timing analysis and validation, ensuring high-quality and reliable chip designs.

Key Responsibilities

• Develop micro-architectures and implement digital designs for complex IP blocks and SoCs.
• Write synthesizable RTL code using Verilog and SystemVerilog.
• Perform design quality checks, including linting, Clock Domain Crossing (CDC) analysis and low-power verification using UPF/CPF.
• Conduct logic synthesis, develop timing constraints and support timing closure activities.
• Work closely with verification engineers to define test plans and ensure design functionality and quality.
• Support pre-silicon validation, post-silicon bring-up and hardware debugging.
• Prepare and maintain design specifications and technical documentation.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering or a related discipline.
• Proven experience in ASIC design flows and digital IC design methodologies.
• Strong proficiency in RTL development using Verilog or SystemVerilog.
• Hands-on experience with logic synthesis, timing analysis and scripting languages such as TCL or Python.
• Knowledge of low-power design techniques and power integrity is an advantage.
• Familiarity with industry-standard EDA tools from Synopsys, Cadence or Siemens.
• Strong analytical, problem-solving and teamwork skills.
• Effective communication skills and the ability to collaborate with global engineering teams.

Interested applicants for the above advertised position(s), please click on the APPLY button below

EA License No: 13C6305

Reg. No.: R1874608 | LEE JIA HOU

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