Digital Mixed Signal Engineer

Lead full-chip mixed-signal verification of SoCs. Build Verilog-AMS/real-number models for ADC, DAC, PLL, bandgap and SerDes. Develop SV/UVM testbenches, drive coverage closure, debug analog-digital issues, automate regressions in Python/TCL.

Required Candidate profile

B.E/B.Tech/M.Tech in Electronics/VLSI with 5-10 yrs in mixed-signal verification. Strong in Verilog-AMS, SystemVerilog/UVM, ADC/DAC, PLL, SerDes. Python/TCL scripting. Strong debug skills.