DSP Firmware Engineer

🚀 DSP Firmware Engineer | Space Sector

📍 Harwell, Manchester or Stevenage | 4 days onsite, 1 day from home

📄 Initial 3-month contract (strong potential for extension)

💷 £550 per day | Inside IR35

🔧 The Role

An exciting opportunity has arisen for an experienced DSP Firmware Engineer to join a leading organisation within the space sector, supporting a 5G-related programme focused on next-generation communications technology.

Working within a multidisciplinary engineering team, you'll develop FPGA firmware using AMD/Xilinx Versal ACAP devices. The programme focuses on high-speed interfaces, with particular interest in JESD, MRMAC and high-speed ADCs/DACs.

You'll contribute across the FPGA development lifecycle, from requirements capture and architectural design through to VHDL implementation, verification, synthesis and hardware validation.

💡 Key Responsibilities

• Capture technical requirements and develop FPGA architectures and block diagrams.
• Design, develop and implement FPGA solutions using VHDL.
• Work with AMD/Xilinx Versal ACAP devices and high-speed interfaces, including JESD and MRMAC.
• Integrate and test high-speed ADCs and DACs.
• Model and simulate DSP/IP blocks using MATLAB and/or Python.
• Develop VHDL testbenches for bit-equivalent verification against test vectors.
• Perform synthesis, place-and-route, timing closure and implementation constraint development.
• Carry out hardware bring-up, testing and validation on target hardware.
• Collaborate with multidisciplinary teams developing telecommunications payloads and sensing technologies.

🧠 What We're Looking For

Core experience:

• Strong FPGA engineering and VHDL development experience.
• RTL design, verification and FPGA implementation.
• Requirements capture and architectural design.
• Synthesis, place-and-route and timing constraints.
• Hardware bring-up, testing and validation.
• Digital Signal Processing (DSP) and/or telecommunications knowledge.

Particularly relevant experience:

• AMD/Xilinx Versal ACAP devices and architectures.
• High-speed interface development and integration, particularly JESD and/or MRMAC.
• Integration, testing or bring-up of high-speed ADCs and DACs.
• 5G telecommunications or related communications systems.
• MATLAB and/or Python for modelling and simulation.

Experience with Versal ACAP and the specific high-speed interface technologies used on the programme would be a significant advantage. Strong FPGA/VHDL engineers with relevant high-speed interface, DSP or telecommunications experience will also be considered.

Additional desirable experience:

• Embedded C++ development, particularly for parallel processing.
• Bare-metal or Embedded Linux development to support testing of programmable logic within an SoC.
• Versal AI Engines.
• Space, aerospace or defence sectors.

🔒 Security Vetting Note

Successful candidates will be required to complete BPSS (Baseline Personnel Security Standard) screening before starting. This includes right-to-work verification, identity checks, a basic criminal record check, employment history verification and reference checks.