DV Engineer

📢 WE’RE HIRING - DV Engineer (Mandarin Speaker Advantage)

Office Location: Bayan Lepas, Penang

Working Hours: 5 Days Per Week, 9am - 6pm (Monday - Friday)

Basis Salary: RM10,000 ~ RM15,000 (based on experiences)

About the role
We are seeking a highly motivated DV Engineer to drive the next generation of AI-assisted silicon development. This role combines traditional RTL design and verification expertise with AI/ML technologies to improve engineering productivity, quality, and development efficiency across the silicon lifecycle. The ideal candidate has a solid foundation in ASIC/SoC design and verification, along with hands-on experience developing or applying AI solutions for engineering workflows.

Key responsibilities

• Develop and maintain high-quality RTL in Verilog/SystemVerilog for ASIC/SoC

products

• Participate in architecture definition, microarchitecture development,

implementation, and integration

• Develop UVM-based verification environments, test plans, testcases, assertions, and

coverage models

• Debug functional, performance, and integration issues across IP, subsystem, and SoC

levels

• Develop AI agents and copilots to accelerate RTL design, verification, debug, code

review, and productivity workflows

ACADEMIC CREDENTIALS:

• BS or above degree in Electrical Engineering, Computer Engineering, Computer

Science, or related field

• Major in Micro-Electronics, Computer Science, or a related discipline

What we're looking for

• 3+ years of experience in ASIC/SoC RTL Design and/or Design Verification

• 1+ year of practical experience applying AI/ML or Generative AI technologies

• Strong knowledge of Verilog/SystemVerilog and RTL design methodologies

• Experience with ASIC/SoC development flow, UVM verification, functional coverage,

and assertions (SVA)

• Experience with Generative AI / LLMs, prompt engineering, and AI agent workflows

• Strong Python programming skills, with experience in Git, Linux, and scripting

automation

• Familiarity with RAG architectures, MCP tools, and frameworks such as LangChain,

LangGraph, AutoGen, or CrewAI

• Familiarity with cloud AI platforms and AI-assisted software development tools

• Experience with industry-standard EDA and simulation/debug tools is a plus

• Apply LLMs and Agentic AI technologies to automate tasks such as RTL

understanding, test plan and assertion generation, coverage analysis, debug triage, and

regression failure root-cause analysis

• Build AI-powered engineering workflows using Python, LangChain, MCP, vector

databases, and modern GenAI platforms

• Collaborate closely with Architecture, Design, DV, Physical Design, Emulation, Post-

Silicon, and Software teams to identify high-impact AI use cases

• Drive AI adoption across silicon engineering teams; share best practices,

methodologies, and reusable AI frameworks

• Mentor engineers on AI-assisted design and verification technologies, and

measure/report productivity improvements enabled by AI solutions

PREFERRED EXPERIENCE:

• Strong cross organizational communication skills

• Highly collaborative

• Ability to work well as a multi-site team

• Ability to multitask

• Problem solving and analytical ability

• Experience in NoC, PCIe, High-Speed Interface IP development

• Experience with synthesis, static timing analysis, and physical design (PD) flows

• Experience building AI tools for RTL generation, verification automation, debug

acceleration, or coverage closure

• Understanding of ML fundamentals, fine-tuning, embeddings, and vector databases

• Experience working in a challenging engineering environment