DV Engineer (SV & UVM)

Job Title: DV Engineer (SV & UVM) - 3-5 Yrs

Location: Hyderabad

No. Of positions: 1

Experience required: 3-5 years

• Must have hands on experience coding in System Verilog /UVM.
• Experience developing testbenches for block level or IP level verification.
• Experience working on subsystem or SoC level would be helpful.
• Candidate should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules.

Job Deliverables

• Developing and maintaining block level test benches.
• V plan, regression and coverage closure
• Work on testbenches with real number modelling.
• Netlist and Gate level simulations

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