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Electro-Optic Link Hardware Engineer

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Onsite

Electro-Optic Link Hardware Engineer

Lightmatter

Electro-Optic Link Hardware Engineer

Skills

PythonMATLABMachine Learning

1 month ago

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Important information


Salary:

$155,000 – $190,000 / year

Location:

San Francisco, CA, USA

Work mode:

Onsite

Published on:

14 October 2026

What they need


Who you are

  • If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders
  • We're looking for a hands-on Photonics engineer to lead verification and characterization of high-speed electro-optic links across multiple silicon and system programs
  • You'll work at the bench alongside the EOE team owning modeling methodology, measurement standards, and serving as the escalation point for the toughest signal integrity and link-performance problems in the org
  • MS/PhD in EE, Photonics, Physics (8+ yrs) or BS/MS (10+ yrs)
  • Ownership of verification strategy for a full silicon/system program
  • Deep expertise in 56G/112G/224G+ serial links, SerDes equalization (CTLE/FFE/DFE), and signal integrity (S-parameters, crosstalk, link budgets)
  • Hands-on lab experience leading investigations that stalled others
  • Strong Python/MATLAB for team-used automation frameworks
  • Proficiency with VNA, scopes, BERTs, TDRs, and tools like ADS, HFSS, Cadence, COMSOL
  • Track record mentoring engineers
  • Silicon photonics/EO systems at the architecture level
  • Package/PCB/channel co-design ownership
  • COM/IBIS-AMI modeling, patents/standards contributions (OIF, IEEE 802.3)

What the job involves

  • Run hands-on lab characterization and debug of high-speed electrical/optical hardware, including novel failure modes
  • Build system-level electrical/optical/EO channel models and correlate them against your own bench measurements
  • Own link budget and verification methodology while staying hands-on with the validating measurements
  • Characterize eye diagrams, BER, jitter, equalization, and channel impairments
  • Support silicon bring-up and root-cause debug with analog, package, PCB, and SerDes teams
  • Influence chip/package/system architecture tradeoffs based on bench findings
  • Mentor Senior/Staff engineers without stepping back from lab work
  • Build automation/tools to speed up characterization work

Benefits

  • Commuter benefit
  • Happy hour -Spend time together and build friendships
  • Generous vacation policy and holidays
  • 401(K)
  • Opportunity to learn from your peers and teach them what you know across electronics, photonics, machine learning, and more

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