Electronic FPGA Engineer

Your tasks

• Design & implement FPGA logic in VHDL for Xilinx Artix-7 devices using Vivado, adhering to coding standards and design reviews.

• Develop finite state machines to control and sequence hardware interfaces and protocols reliably.

• Create low-level driver logic for I C, SPI (and other simple serial interfaces), including initialisation, transaction handling, and error conditions.

• Write and maintain test benches (self-checking where practical), conduct functional and timing simulations, and document verification results.

• Perform hardware bring-up and validation, including lab testing, measurements, and iterative debug; collaborate on board-level constraints and interface timing.

• Manage constraints (XDC), clocking, resets, and CDC analysis; achieve timing closure and generate production-ready bitstreams.

• Contribute to requirements capture, architecture design, module specifications, and DFT/DFM considerations for FPGA-based systems.

• Maintain configuration management (SVN), branching/release processes, and traceability to requirements.

• Produce and maintain technical documentation: design descriptions, registers/interfaces, test procedures, and change logs.

• Participate in design and code reviews, support system integration, and assist production/field teams with issue triage.

• Support continuous improvement of FPGA design flows, test coverage, and automation (e.g., Tcl/Python scripts).

Your profile

• Degree or equivalent experience in Electronic/Electrical Engineering, Computer Engineering, or related discipline.

• Strong hands-on experience with VHDL for FPGA design and verification.

• Proven experience targeting Xilinx Artix-7 families; confident using Vivado (project setup, constraints, synthesis, place & route, timing closure, bitstream generation).

• Ability to design deterministic finite state machines (FSMs) for control/driver logic.

• Experience implementing and validating low-level embedded interfaces: I C, SPI, UART (desirable), including bus arbitration, timing, and protocol edge cases.

• Competence in writing self-checking test benches and performing simulation (e.g., using Vivado simulator).

• Experience testing on hardware: bringing up boards, using logic analysers/oscilloscopes, debugging timing/constraint issues, and validating firmware in-system.

• Understanding of timing constraints (XDC), clock domain crossing (CDC), metastability, resets, and synchronous design best practices.

• Familiarity with version control (e.g., SVN).

• Optional but beneficial: knowledge of PCB-level considerations, signal integrity, and simple scripting (Tcl/Python) to automate flows.

• Typically 3+ years in FPGA development within a product or R&D environment (or demonstrable equivalent).

Track record of delivering FPGA features/modules from requirements through to validated hardware.

• Experience collaborating with electronics engineers and embedded software engineers for system integration.

• Clear communicator with strong documentation habits (design specs, interface descriptions, test plans, release notes).

• Methodical problem-solver with attention to detail; able to work independently and in cross-functional teams.

• Ownership mindset with a focus on reliability, maintainability, and testability.

Why HUBER+SUHNER Polatis

Our aim is to be the employer of choice and as such you can be assured of a market leading remuneration package that matches your skills and experience.

Your employment and development is at the heart of our "Fundamentals".

We have an entrepreneurial and collaborative culture within the business.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

Disclaimer: The job location mentioned in this description is based on publicly available information or company headquarters. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.