Wipro
Emulation Architect (ZeBu / HAPS)
Skills
5 days ago
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Important information
Contract type:
Permanent
Location:
Bengaluru, Karnataka, India
Work mode:
Hybrid
Published on:
19 October 2026
What they need
Greetings from Wipro
We are pleased to share an exciting opportunity for the Emulation Architect (ZeBu / HAPS) role at Wipro. Please find the role details below and share your updated resume at [email protected]
Role Details
Requirement Name : Emulation Architect (ZeBu / HAPS)
Experience:12Years +
Work location : Bengaluru / Hyderabad / Kochi / Chennai / Any LocationWork Mode : Hybrid
Job Type: Full-Time with Wipro
JD
What You Bring(Mandatory:
- 15+ years in ASIC/SoC pre-silicon validation, with 8+ years of hands-on ZeBu and HAPS emulation / prototyping.
- Proven delivery of multiple SoC emulation or prototyping programs, from compile through system bring-up.
- Expert in design partitioning, FPGA-friendly RTL, clock and memory mapping, and emulation timing closure.
- Strong with AMBA (AXI/AHB/APB), PCIe, Ethernet, USB and DDR/LPDDR subsystems and their emulation models.
- Experience with ARM- or RISC-V-based SoC bring-up, firmware integration and OS boot on emulators.
- Scripting and automation in Python, Tcl or Perl; ability to debug at waveform, trace and system level.
What You Will Do:
- Define emulation and prototyping strategy: platform selection (ZeBu / HAPS), capacity planning and milestones.
- Own design partitioning, multi-FPGA / multi-board mapping, clocking, timing and interconnect for emulation targets.
- Drive ZeBu and HAPS compile flows, bring-up, runtime performance and debug visibility.
- Build transactor, co-emulation and virtual-platform environments for firmware, OS and system-level validation.
- Run hardware/software co-validation, power and performance analysis, and regression automation on emulators.
- Partner with RTL, DV, DFT and SW teams; mentor emulation engineers and lead customer technical reviews.
Good to Have :
- Palladium or Veloce exposure
- Hybrid emulation, virtual platforms and transaction-level co-simulation
- Post-silicon bring-up and chiplet / multi-die validation
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