Emulation Prototyping Engineer

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

Role Summary The Emulation Lead is responsible for driving pre-silicon validation and performance analysis of complex Data Center SoCs using hardware emulation platforms. This role ensures early software bring-up, system-level validation, and debug of critical features before tape-out. The position involves architecting emulation strategies, building scalable environments, integrating IPs and subsystems, and enabling workloads representative of real data center use cases.

Key Responsibilities

• Define emulation methodology for data center SoCs with CPU, NOC/Crossbar, Ethernet and high-speed IOs.
• Develop partitioning strategies& set up emulation environments (Palladium, Veloce, ZeBu) and partition RTL for hardware-based platforms.
• Port large-scale SoCs/IPs onto emulators, bring up the platform, and debug interface/functional issues involving firmware/hardware.
• Integrate and develop synthesizable monitors/checkers, VIP transactors,NOC bridges (MAC/PHY DDR)
• Emulation prototyping forboot loader bring-up, SoC configuration, first power-on sequences, clock/reset validation, strap/fuse programming
• Own stress testing and completeness of data path includingEthernet PHY/MAC link bring-up, loopback tests; validate DMA descriptors, interrupts
• Automate emulation regression flows using scripting (TCL, Python, Perl) andoptimize for coverage and debug time.
• Collaborate closely with verification, firmware, software, architecture teams for pre-silicon validation and bring-up.

Required Skills

• Strong exposure of emulation platformCadence Palladium, Synopsys ZeBu, Mentor Veloce
• Strongproficiency in C/C++ and RTL partitioning for emulation platforms.
• Drive validation activitiesex: bootloader bring-up and executing real-world workloads.
• Waveform analysis, transaction-level debug, log parsing
• Emulation + virtual models, FPGA prototyping.

Added Advantage

• Understanding of System Verilog/UVM, SVA, coverage-driven verification
• Python/TCL scripting experience and post-silicon bring-up