Engineer II – DFT

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Job Description

• We are looking for a highly motivated DFT / ATPG Engineer with 2+ years of experience in SoC/ASIC test methodology, ATPG, scan and MBIST. The candidate should have strong hands-on expertise in DFT implementation on hierarchical designs and good experience with Tessent/Modus tools for ATPG, MBIST, and diagnosis.

In addition to core DFT responsibilities, this role will also contribute to DFT automation flow development using Python and support contemporary AI-based technical initiatives internally within Microchip , aimed at improving productivity, debug efficiency, and overall flow quality.

Key Responsibilities

• Develop and maintain Python-based automation flows and utilities for DFT setup, pattern generation support, report parsing, coverage analysis, debug, and productivity improvement.
• Contribute to flow development and automation infrastructure to improve ATPG execution efficiency and methodology reuse across projects.
• Support and participate in internal AI-driven technical initiatives related to DFT/ATPG automation, debug assistance, data analysis, and engineering productivity improvement within Microchip.
• Handle DFT implementation and support for hierarchical designs.
• Work on Tessent/Modus ATPG flow for DFT setup, pattern generation, validation, and coverage analysis.
• Support Tessent/Modus MBIST flow for MBIST hardware generation and integration.
• Use Tessent/Modus diagnosis tools for failure analysis and on-silicon debug.
• Perform scan pattern simulation, debug, and pattern validation.
• Support ATPG pattern delivery to the Test Engineering / ATE team.
• Debug simulation and DFT issues at block and SoC level.
• Collaborate with CAD, Design, STA, Product Engineering, and Test teams to drive DFT solutions and new initiatives.

Requirements/Qualifications

• 2+ years of experience in DFT / ATPG engineering.
• Strong hands-on experience in scan pattern simulation and debug.
• Strong knowledge of Python scripting for automation, flow development, and methodology enhancement.
• Interest or exposure in applying AI/ML-based engineering techniques for automation, debug, or data analysis is a plus.
• Good written and verbal communication skills.
• Hands-on expertise in handling DFT on hierarchical designs.
• Strong experience with Tessent and/or Cadence Modus ATPG tools for DFT setup and pattern generation.
• Experience with Tessent/Modus MBIST tools for MBIST hardware generation.
• Experience with Tessent/Modus diagnosis tools for on-silicon debug.

Preferred Skills

• Familiarity with Perl, Tcl, or Shell scripting is a plus.
• Strong problem-solving and debugging skills.
• Self-motivated team player with the ability to work across cross-functional teams.

Travel Time 0% - 25%

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