Founding MTS: Logic Design & Verification

Founding MTS for agentic AI in logic design & verification: build systems to generate, review, simulate, debug, and validate RTL; integrate IPs/protocols PCI, Ethernet ; and connect agents to simulators, formal, synthesis, and verification tools.

Required Candidate profile

BS/MS CS, EE
RTL design, verification, FPGA/ASIC flows, SoC/IP integration, Verilog/SV, simulation, testbenches, assertions, debugging, AXI, PCIe, Ethernet, Memory, python
Challenges at Agentic AI