Fpga Design Engineer

Role & responsibilities

1. Excellent understanding of PDCP layer 3GPP specifications

2. Development of High level architecture and Microarchitecture from Specifications

3. Proficiency in HDL languages Verilog/VHDL/System Verilog

4. A clear understanding of FPGA design elements like signal integrity, clock networks, clock-domain crossing, resource management, physical and timing constraints, static timing analysis, packet buffering, design closure techniques for area/timing/power etc is highly preferred

5. Domain knowledge of Ethernet/4G/5G standards is highly preferred

6. Micro-architect features to meet performance, throughput, latency and area requirement.

7. Experience in XILINX tool- Vivado/VITIS

8. Must have worked on STA and constraints development

9. Hands on Experience on PCIe, Ethernet, DDR4/5 , AMBA AXI 4, APB bus protocols

10. Excellent interpersonal and team skills ,able to work independently and able to problem solve complex, unique and detailed issues

11. Excellent hands-on debug skills and problem-solving attitude.

12. Expertise in bug fixing, RTL code integration, board validation and testing

Preferred candidate profile