FPGA / RTL Design Engineer

Experience – 2 to 5 years of experience in FPGA/RTL design and development.

Qualification: B.E./B.Tech in Electronics & Communication / Electrical & Electronics Engineering.

Strong programming and RTL design skills in Verilog/SystemVerilog/VHDL, with experience in FPGA design, simulation, synthesis, timing analysis and debugging.

Hands-on experience with AMD/Xilinx FPGAs, RFSoC or Intel/Altera FPGAs, including Vivado, Vitis, Quartus Prime and FPGA IP integration.

Experience in interfacing High-Speed ADC/DACs, including JESD204B/JESD204C or similar high-speed serial interfaces.

Experience in implementing DSP algorithms on FPGA, including FFT, digital filters, DDC/DUC, channelization and high-speed signal-processing pipelines.

Knowledge of 10 Gigabit Ethernet, high-speed transceivers, AXI interfaces, DMA and high-throughput data transfer architectures.

Experience in FPGA hardware bring-up, timing closure, clocking, ILA-based debugging and hardware-software integration.

Knowledge of Radar, Electronic Warfare, Digital Signal Processing or Defence Electronics will be an added advantage.

Strong analytical, debugging and problem-solving skills with an interest in developing FPGA/RFSoC-based Radar, EW and Defence systems.

Location: Bengaluru
Interested candidates: Please share your CV / apply through our website at www.diisha.com with Job ID: 1003

Be part of the team building next-generation Radar and Defence technologies.

Pay: ₹400,000.00 - ₹800,000.00 per year

Education:

• Bachelor's (Preferred)

Experience:

• FPGA: 2 years (Required)

Work Location: In person