FPGA Verification Engineer

Job Title: FPGA Verification Engineer (3-5 Years)

No. Of Positions: 4

Work Location: Bangalore

Role Overview

We are looking for a detail-oriented FPGA Verification Engineer with 3 to 5 years of experience to build advanced verification environments and ensure the functional correctness of complex FPGA designs. You will be responsible for creating testbenches, writing test cases, and achieving high code and functional coverage.

Key Responsibilities

1. Verification Environment Development: Develop and maintain scalable, reusable verification environments using SystemVerilog and UVM (Universal Verification Methodology).
2. Test Planning & Execution: Create comprehensive test plans from architectural specifications. Write test cases, sequences, and checkers to thoroughly verify complex RTL designs.
3. Protocol Verification: Verify complex bus architectures and communication interfaces, including AMBA (APB, AHB, AXI), Ethernet, and serial protocols (I2C, SPI, UART).
4. Coverage & Debug: Analyze functional and code coverage metrics to identify verification holes. Debug simulation mismatches and work closely with RTL designers to root-cause bugs.
5. Regression Management: Set up and maintain automated regression test suites for continuous integration (CI) pipelines.

Required Qualifications & Skills

1. Experience: 3 to 5 years of professional experience in FPGA/ASIC functional verification.
2. Methodologies & Languages: Strong expertise in SystemVerilog, UVM, and assertion-based verification (SVA).
3. Protocol Knowledge: Solid grasp of communication protocols such as AMBA APB, AHB, AXI, Ethernet, and serial protocols (I2C, SPI, UART).
4. Simulation Tools: Hands-on experience with industry-standard simulators (e.g., Siemens Questa, Synopsys VCS, or AMD/Xilinx Vivado Simulator).
5. Scripting: Proficiency in Python, Tcl, or Bash for automation and scripting tasks.

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